1. Field of the Invention
The present invention relates to a driving circuit for a display apparatus, particularly to a driving circuit for a display apparatus with a multitude of outputs that outputs specified waveforms and is useful for scaling down the driver chip.
Various kind of driver chips generally output specified waveforms, which are formed in such a way that a plurality of power supplies associated with the respective waveforms are selected by transfer gates and then outputted.
In a driver chip with a multitude of outputs such as a liquid crystal driver, smaller output impedance is needed to obtain a larger driving capability, thus a chip area used for the above mentioned transfer gates tends to be large thus occupying a large percentage of the whole chip area.
Furthermore, recently, as the screen of liquid crystal displays have become wider, driving load requirements have become larger. This necessitates even smaller output impedance, thus the transfer gates will occupy an even greater percentage of the whole chip area.
On the other hand, the reduced chip area of a driving circuit has continuously been sought and crucial to realize even lower price.
For reference purposes, a liquid crystal display apparatus as disclosed in the Japanese Patent Open-Laying No. Hei 2-157815 will be explained below.
FIG. 5 is a circuit diagram of the liquid crystal display apparatus. Elements 4, 8 and 12 are liquid crystal elements, 1 is a video signal line for controlling the twist of the liquid crystal elements 4, 8 and 12 and so on. Elements 3, 7 and 11 are thin film transistors (hereafter referred to as TFT's) for controlling the transfer of a video signal in the video signal line 1 to the liquid crystal elements 4, 8 and 12. Elements 2, 6, and 10 are scanning signal lines for turning on or off TFT's 3, 7 and 11. Elements 5, 9 and 13 are storage capacitors for storing charge.
It should be noted that FIG. 5 illustrates only part of the liquid crystal display apparatus. In accordance with resolution of the display apparatus, a specified number of combinations of a TFT, a liquid crystal element and a storage capacitor are actually arrayed vertically and horizontally, and a specified number of video signal lines and scanning signs lines are also disposed.
FIG. 6 shows the waveforms of scanning signals used in the liquid crystal display apparatus of FIG. 5. A scanning signal 2S comes in a scanning signal line 2, a scanning signal 6S in a scanning signal line 6 and a scanning signal 10S in a scanning signal line 10.
This liquid crystal display apparatus features the presence of the storage capacitors 5, 9 and 13, and as a result of a stored charge on the storage capacitors 5, 9 and 13 an even smaller amplitude of a video signal on the video signal line 1 is usable, thereby helping decreasing power consumption.
The performance of the liquid crystal display apparatus will be explained below in detail.
During t1, scanning signals 2S, 6S and 10S as respectively inputted to the scanning signal lines 2, 6 and 10 turn off the respective TFT's 3, 7 and 11.
During t2, the scanning signal 2S inputted to the scanning signal line 2 turns on the TFT 3, but the amplitude of a video signal on the video signal line 1 is too small to activate the liquid crystal element 4, and the voltage on the video signal line 1, which is to be used to activate the liquid crystal element 4, is applied to the storage capacitor 5, producing a potential difference between the terminals of the storage capacitor 5.
During t3, the scanning signal 2S inputted to the scanning signal line 2 turns off TFT 3.
During t4, the scanning signal 6S inputted to the scanning signal line 6 turns on TFT 7, but the amplitude of the video signal on the video signal line 1 is too small to activate the liquid crystal element 8, and the voltage on the video signal line 1, which is to be used to activate the liquid crystal element 8, is applied to the storage capacitor 9, producing a potential difference between the terminals of the storage capacitor 9.
During t5, the scanning signal 6S inputted to the scanning signal line 2 turns off TFT 7.
During t6, the scanning signal 2S inputted to the scanning signal line 2 activates and twists the liquid crystal element 8.
In more detail, as the potential of the scanning signal line 2 is increased, the potential of the liquid crystal element 8 is increased to the sum of the potential of the scanning signal line 2 and the potential difference (namely, the voltage of the video signal line 1 as stored) between the terminals of the storage capacitor 9. For this reason, even a small amplitude of the video signal on the video signal line 1 is able to activate the liquid crystal element 8.
However, unless TFT 7 is turned off at this time, charge stored in the storage capacitor 9 would discharge to the video signal line 1. For this reason, a time interval t5 is provided so that the potential of the scanning signal line 2 is to be increased after TFT 7 is turned off.
During t6, when the scanning signal 10S is inputted to the scanning signal line 10, the video signal on the video signal line 1 is stored in the storage capacitor 13. Here it should be noted that this video signal on the video signal line 1 is of inverse polarity to that stored in the storage capacitor 9.
During t7, the scanning signal 10S inputted to the scanning signal line 10 turns off TFT 11.
During t8, the scanning signal 6S inputted to the scanning signal line 6 activates and twists the liquid crystal element 12.
In more detail, as the potential of the scanning signal line 6 is lowered, the potential of the liquid crystal element 12 is decreased to the sum of the potential of the scanning signal line 6 and the potential difference between the terminals of the storage capacitor 13. For this reason, even a small voltage amplitude of the video signal on the video signal line 1 is able to activate the liquid crystal element 12. In this case the liquid crystal element 12 twists in the inverse direction against the liquid crystal element 8.
The above mentioned operations are to be repeated until the n-th scanning signal is generated (not shown in FIG. 6), thereby displaying one image on the liquid crystal display apparatus.
If liquid crystal is being twisted in one direction for a long time, a burning effect would occur. Therefore, even when displaying the same image the direction of twisting needs to be incessantly and completely inverted. The performance for twisting liquid crystal in the inverse direction will be explained below.
During t12, the scanning signal 2S inputted to the scanning signal line 2 turns on TFT 3, but the voltage amplitude of a video signal inputted to the video signal line 1 is too small to activate the liquid crystal element 4. However, the voltage of the video signal line 1 which is to be used to activate the liquid crystal element 4 is applied to the storage capacitor 5, thereby producing the potential difference between the terminals of the storage capacitors 5. Here, during t2, the voltage of the video signal line 1 is of opposite polarity to that applied to the storage capacitor 5.
During t13, the scanning signal 2S inputted to the scanning signal line 2 turns off TFT 3.
During t14, the scanning signal 6S inputted to the scanning signal line 6 turns on TFT 7, but the voltage amplitude of a video signal on the video signal line 1 is too small to activate the liquid crystal element 8. However, the voltage of the video signal line 1 which is to be used for activating the liquid crystal element 8 is applied to the storage capacitor 9, thereby producing the potential difference between the terminals of the storage capacitor 9. Here it should be noted that during t14, the potential of the video signal line 1 is of opposite polarity to that applied to the storage capacitor 9.
During t15, the scanning signal 6S inputted to the scanning signal line 6 turns off TFT 7.
During t16, when the scanning signal 2S is inputted to the scanning signal line 2, the liquid crystal element 4 is activated and twisted.
In more detail, as the potential of the scanning signal 2S is lowered, the potential of the liquid crystal element 8 is decreased to the sum of the potential of the scanning signal line 2 and the potential difference between the terminals of the storage capacitor 9. For this reason, even a small voltage amplitude of the video signal on the video signal line 1 is able to activate the liquid crystal element 8.
However, unless TFT 7 is turned off at this time, charge stored in the storage capacitor 9 would discharge via the video signal line 1. For this reason, a time interval t15 is provided so that after TFT 7 is turned off the potential of the scanning signal line 2 is decreased. During t13, when the scanning signal 10S is inputted to the scanning signal line 10, the voltage of the video signal line 1 is stored in the storage capacitor 13. Here it should be noted that the potential of the video signal line 1 is of opposite polarity to that applied to the storage capacitor 13.
During t17, the scanning signal 10S inputted to the scanning signal line 10 turns off TFT 11.
During t18, the scanning signal 6S inputted to the scanning signal line 6 activates and twists the liquid crystal element 12.
In more detail, as the potential of the video signal 6 is increased, the potential of the liquid crystal element 12 is decreased to the sum of the potential of the scanning signal line 6 and the potential difference between the terminals of the storage capacitor 13. For this reason, even a small voltage amplitude of the video signal on the video signal line 1 is able to activate the liquid crystal element 12.
The above mentioned operations are to be repeated until the n-th scanning signal is generated (not shown in FIG. 6), thereby twisting in the inverse direction all liquid crystal elements in the liquid crystal display apparatus.
2. Description of the Prior Art
As described above, this liquid crystal display apparatus intends to reduce power consumption by making use of charge stored in the storage capacitors 5, 9 and 13, and for this purpose a driving circuit that outputs the waveforms as shown in FIG. 6 is needed.
Referring to FIG. 6, a conventional driving circuit that outputs the waveforms as shown in FIG. 6 for the liquid crystal display apparatus will be explained.
FIG. 7 is a circuit diagram of a conventional driving circuit with n pieces of output terminals for the liquid crystal display apparatus.
In FIG. 7, 30 and 31 are P-type MOS transistors, 32 to 34 are N-type MOS transistors, 35 and 36 are inverter circuits for inverting an input signal, 50 to 53 are control signal lines for turning on or off transistors 30, 31, 32, 33 and 34. 45 is an output terminal for outputting a driving signal into the scanning signal line 2 in the liquid crystal display apparatus as shown in FIG. 5. 40 to 43 are potential supply lines for supplying potentials to the output terminals when the respective transistors 30, 31, 32, 33, 34, 60 and so on, are in the on-state, 40 is an on potential line for supplying a TFT in the liquid crystal display apparatus with an on potential VDD1, 41 and 42 are storage potential lines for supplying a storage capacitor with respective potentials VDD2 and VDD4 to store charge, and 43 is an off potential line for supplying a TFT with an off potential VDD3.
Here, the following relationship holds: VDD1&gt;VDD2&gt;VDD3&gt;VDD4&gt;=VSS.
60 and 61 are P-type MOS transistors, 62 to 64 are N-type MOS transistors, 65 and 66 are inverter circuits for inverting an input signal, 70 to 73 are control signal lines for turning on or off transistors 60, 61, 62, 63 and 64. 75 is an output terminal for outputting a driving signal into the scanning signal line 6 in the liquid crystal display apparatus as shown in FIG. 5.
FIG. 8 is a timing chart of a driving circuit for the liquid crystal display apparatus, where 50S to 53S and 70S to 73S show input waveforms on the control signal lines 50 to 53 and 70 to 73, respectively, and 45S and 75S are output waveforms from the output terminals 45 and 75, respectively, as shown in FIG. 7.
The operation of the driving circuit for the liquid crystal display apparatus as shown in FIG. 7 will be explained, referring to FIG. 8.
During t1, when control signals 50S to 53S are inputted to control signal lines 50 to 53, respectively, as the control signal 53S has a voltage level "1", the N-type MOS transistor 34 is turned on, then the off potential on the off potential line 43 is outputted from the output terminal 45, namely, a driving signal 45S is outputted from the output terminal 45.
On the other hand, when control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 73S has a voltage level "1", the N-type MOS transistor 64 is turned on, then the off potential on the off potential line 43 is outputted from the output terminal 75, namely, a driving signal 75S is outputted from the output terminal 75.
During t2, when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 50S has a voltage level "1", the P-type MOS transistor 30 is turned on, then the on potential on the on potential line 40 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, even when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 73S retains a voltage level "1", the off potential on the off potential line 43 is outputted from the output terminal 75. (Refer to the driving signal 75S from the output terminal 75 in FIG. 8).
During t3, when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 52S has a voltage level "1", the N- MOS transistor 33 is turned on, then the storage potential VDD4 on the storage potential line 42 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 73S retains a voltage level "1", then the off potential on the off potential line 43 is outputted from the it output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t4, even when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 52S retains a voltage level "1", the storage potential VDD4 on the storage potential line 42 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 70S has a voltage level "1", the P-type MOS transistor 60 is turned on, then the on potential on the on potential line 40 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t5, when the control signals SOS to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 52S retains a voltage level "1", then the storage potential VDD4 on the storage potential line 42 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 71 has a voltage level "1", a CMOS transistor comprising the P-type MOS transistor 61 and the N-type MOS transistor 62 is turned on, then the storage potential VDD2 on the storage potential line 41 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t6, when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, as the control signal 53S has a voltage level "1", the off potential on the off potential line 43 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, even when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 71S retains a voltage level "1", the storage potential VDD2 on the storage potential line 41 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t7, even when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 53S has a voltage level "1", the off potential on the off potential line 43 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signal 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 71S has a voltage level "1", the storage potential VDD 2 on the storage potential line 41 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75).
The above mentioned operations are to be repeated up until the n-th output terminal (not shown in FIG. 7), thereby outputting the scanning signals for displaying one image in the liquid crystal display apparatus.
Next, liquid crystal in the liquid crystal display apparatus is twisted in the inverse direction to avoid a burning effect in the following manner.
During t12, when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 50S has a voltage level "1", the P-type MOS transistor 30 is turned on, then the on potential on the on potential line 40 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, even when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 73S has a voltage level "1", the off potential on the off potential line 43 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t13, when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 51S has a voltage level "1", a CMOS transistor comprising the P-type MOS transistor 31 and the N-type MOS transistor 32 is turned on, then the storage potential VDD2 on the storage potential line 41 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, even when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 73S retains a voltage level "1", then the off potential on the off potential line 43 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t14, even when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 51S retains a voltage level "1", the storage potential VDD2 on the storage potential line 41 is outputted from the output terminal 45. (Refer to the wave form of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 70S has a voltage level "1", the P-type MOS transistor 60 is turned on, then the on potential on the on potential line 40 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t15, even when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 51S retains a voltage level "1", then the storage potential VDD2 on the storage potential line 41 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signals 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 72S has a voltage level "1", the N-type MOS transistor 63 is turned on, then the storage potential VDD4 on the storage potential line 42 is outputted from the output terminal 75. (Refer to the driving signal 75S from the output terminal 75 in FIG. 8).
During t16, when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 53S has a voltage level "1", the N-type MOS transistor 34 is turned on, then the off potential VDD3 on the off potential line 43 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S in FIG. 8).
On the other hand, even when the control signal 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 72S has a voltage level "1", the storage potential VDD4 on the storage potential line 42 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75 in FIG. 8).
During t17, even when the control signals 50S to 53S are inputted to the control signal lines 50 to 53, respectively, as the control signal 53S has a voltage level "1", the off potential on the off potential line 43 is outputted from the output terminal 45. (Refer to the waveform of the driving signal 45S from the output terminal 45 in FIG. 8).
On the other hand, when the control signal 70S to 73S are inputted to the control signal lines 70 to 73, respectively, as the control signal 72S has a voltage level "1", the storage potential VDD4 on the storage potential line 42 is outputted from the output terminal 75. (Refer to the waveform of the driving signal 75S from the output terminal 75).
The above mentioned operations are to be repeated up until the n-th output terminal (not shown in FIG. 7), thereby outputting the scanning signals for displaying one image in the liquid crystal display apparatus.